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advance information powernp tm npe405l embedded processor data sheet 1 features ibm powerpc tm 405 32-bit risc processor core operating up to 266 mhz pc-100 synchronous dram (sdram) interface operating up to 133 mhz - 32-bit interface for non-ecc applications - 40-bit interface serves 32 bits of data plus 8 check bits for ecc applications external peripheral bus - flash rom/boot rom interface - direct support for 8-, or 16-bit sram and external peripherals - up to 4 banks dma support for external peripherals, internal uarts and memory - scatter-gather chaining supported - four channels 2 ethernet 10/100mbps (full-duplex) units with a choice of mii, rmii, or smii interfaces. hdlc interface with 32 channels through 2 ports programmable interrupt controllers supports interrupts from a variety of sources - seven external and 29 internal - edge triggered or level-sensitive - positive or negative active - non-critical or critical interrupt to processor core - programmable critical interrupt priority ordering - programmable critical interrupt vector for faster vector processing programmable timers two serial ports (16550 compatible uart) one iic (i 2 c) interface general purpose i/o (gpio) available supports jtag for board level testing internal processor local bus (plb) runs at sdram interface frequency description designed specifically to address embedded applications, the npe405l provides a high- performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and intrinsically lower power dissipation requirements. this chip contains a high-performance risc processor core, sdram controller, ethernet interfaces, hdlc interface, control for external rom and peripherals, dma with scatter-gather support, serial ports, iic interface, and general purpose i/o. technology: ibm cmos 6sf 0.25 m (0.18 m l eff ) package: 324-ball (23mm) enhanced plastic ball grid array (e-pbga) power (estimated): typical 1.1w, maximum ?.?w while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
advance information powernp tm npe405l embedded processor data sheet 2 contents ordering, pvr, and jtag information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 address map support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 hdlcex interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10/100 mbps ethernet mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
advance information powernp tm npe405l embedded processor data sheet 3 tables sysmem memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dcr address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 sysclk and memclk timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 i/o specifications?00mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 i/o specifications?66mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figures npe405l embedded controller functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 23mm, 324-ball e-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
advance information powernp tm npe405l embedded processor data sheet 4 ordering, pvr, and jtag information this section provides the part numbering nomenclature for the npe405l. for availability, contact your local ibm sales office. the part number contains a part modifier. this modifier provides for identification of future enhancements (for example, higher performance). each part number also contains a revision code. this refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. the pvr (processor version register) is software accessible and contains additional information about the revision level of the part. refer to the npe405l user? manual for details on the register content. ibm part number key product name order part number 1 processor frequency package rev level pvr value jtag id npe405l 200mhz 23mm, 324 e-pbga 0x416100c0 0x???????? npe405l 200mhz 23mm, 324 e-pbga 0x416100c0 0x???????? npe405l 266mhz 23mm, 324 e-pbga 0x416100c0 0x???????? npe405l 266mhz 23mm, 324 e-pbga 0x416100c0 0x???????? note 1: z at the end of the order part number indicates a tape and reel shipping package. otherwise, the chips are shipped in a tray. ibm part number ibm25npe405l-3da200cx package (e-pbga) processor speed grade 3 reliability case temperature range revision level shipping package* * blank = tray z = tape and reel (-40? to +85?)
advance information powernp tm npe405l embedded processor data sheet 5 npe405l embedded controller functional block diagram the npe405l is designed using the ibm microelectronics blue logic tm methodology in which major functional blocks are integrated to create an application-speci? asic product. this approach provides a consistent way to generate complex asics using ibm coreconnect tm bus architecture. note: ibm coreconnect busses provide: 64-bit plb interfaces up to 133mhz 32-bit opb interfaces up to 66mhz address map support the npe405l incorporates two simple and separate address maps. the first is a fixed processor address map that serves the powerpc family of processors. this address map defines the possible contents of various address regions which the processor can access. the second address map is for device configuration registers (dcr). this address map is accessed by software running on the npe405l processor through the use of mtdcr and mfdcr commands. ppc405 processor core dcu icu dcr bus 16kb on-chip peripheral bus (opb) gpio iic uart dma bridge processor local bus (plb) sdram external bus controller controller clock control reset power mgmt jtag trace timers mmu controller opb interrupt controller arb - 28-bit addr - 13-bit addr - 32-bit data universal i-cache 8kb d-cache (4-channel) dcrs 133 mhz max 66 mhz max see peripheral interface clock timing table mal8 ethernet hdlcex 32 channels 2 ports x2 x2 - 16-bit data x2 zmii mii, rmii, smii mal64
advance information powernp tm npe405l embedded processor data sheet 6 sysmem memory address map 4gb system memory function sub function start address end address size local memory/peripherals 1 00000000 7fffffff 2gb reserved 80000000 ef5fffff 1.74gb internal peripherals total ef600000 efffffff 10mb uart0 ef600300 ef600307 8b reserved ef600308 ef6003ff uart1 ef600400 ef600407 8b reserved ef600408 ef6004ff iic0 ef600500 ef60051f 32b reserved ef600520 ef6005ff opb arbiter ef600600 ef60063f 64b reserved ef600640 ef6006ff gpio controller registers ef600700 ef60077f 128b reserved ef600780 ef6007ff ethernet 0 controller registers ef600800 ef6008ff 256b ethernet 1 controller registers ef600900 ef6009ff 256b reserved ef600a00 ef600c0f . zmii ef600c10 ef600c1f 16b reserved ef600c20 ef60ffff hdlcex ef610000 ef61ffff 64kb reserved ef620000 efffffff expansion rom 2 f0000000 ffdfffff 254mb boot rom 2, ffe00000 ffffffff 2mb notes: 1. the local memory/peripheral area of the memory map can be configured for sdram, rom or peripherals. 2. the boot rom and expansion rom area of the memory map are intended for use by rom or flash-type devices. while locating volatile sdram and sram in this region is supported by the controller it is not recommended that these regions be used for this purpose.
advance information powernp tm npe405l embedded processor data sheet 7 dcr address map 4kb device configuration register function base address strap/parameter start address(0:9) end address(0:9) size dcr address space 1 000 3ff 1kw (4kb) 1 reserved 000 00f 16w memory controller registers 010 011 2w external bus controller registers 012 013 2w reserved 014 07f 108w plb registers 080 08f 16w reserved 090 09f 16w opb bridge out registers 0a0 0a7 8w reserved 0a8 0af 8w clock, control and reset 0b0 0b7 8w power management 0b8 0bf 8w interrupt controller 0 0c0 0cf 16w interrupt controller 1 0d0 0df 16w reserved 0e0 0ef 16w miscellaneous 0f0 0ff 16w dma controller registers 100 13f 64w reserved 140 17f 64w mal8 registers (ethernet) 180 1ff 128w mal64 registers (hdlcex) 200 27f 128w reserved 280 3ff 384w notes: 1. dcr address space is addressable with up to 10 bits (1024 or 1k unique addresses). each unique address represents a single 32-bit (word) register, or 1 kiloword (kw) (which equals 4 kb).
advance information powernp tm npe405l embedded processor data sheet 8 sdram memory controller the npe405l memory controller core provides a low latency access path to sdram memory. a variety of system memory configurations are supported. the memory controller supports up to four logical banks. up to 256mb per bank are supported, up to a maximum of 1gb. memory timings, address and bank sizes, and memory addressing modes are programmable. features include: 11x8 to 13x11 addressing for sdram (2- and 4-bank) memory bus operates at same frequency as plb 32-bit memory interface support programmable address compare for each bank of memory - 4gb of address space industry standard 168-pin dimms are supported (some con?urations) up to 133mhz memory, includes pc133 support 4mb to 256mb per bank programmable address mapping and timing auto refresh page mode accesses with up to 4 open pages sync dram con?uration via mode set command power management (self-refresh) error checking and correction (ecc) support - standard sec/ded coverage - aligned nibble error detect - address error logging - mixed ecc/non-ecc banks - bypass mode external peripheral bus controller (ebc) up to four rom, eprom, sram, flash, and slave peripheral i/o banks supported up to 66mhz operation burst and non-burst devices 8-, 16-bit byte-addressable data bus width support latch data on ready, synchronous or asynchronous
advance information powernp tm npe405l embedded processor data sheet 9 programmable 2k clock time-out counter with disable for ready programmable access timing per device - 256 wait states for non-burst - 32 burst wait states for ?st access and up to 8 wait states for subsequent accesses - programmable cson, csoff relative to address - programmable oeon, weon, weoff (1 to 4 clock cycles) relative to cs programmable address mapping peripheral device pacing with external ?eady dma controller supports the following transfers: - memory-to-memory transfers - buffered peripheral to memory transfers - buffered memory to peripheral transfers four channels scatter/gather capability for programming multiple dma operations 8-, 16-, 32-bit peripheral support (opb and external) 32-bit addressing address increment or decrement internal 32-byte data buffering capability supports internal and external peripherals support for memory mapped peripherals support for peripherals running on slower frequency buses uart two 8-pin uart interfaces provided selectable internal or external serial clock to allow wide range of baud rates register compatibility with ns16550 register set complete status reporting capability transmitter and receiver are each buffered with 16-byte fifos when in fifo mode fully programmable serial-interface characteristics supports dma using internal dma engine
advance information powernp tm npe405l embedded processor data sheet 10 iic bus interface compliant with phillips?semiconductors i 2 c speci?ation, dated 1995 operation at 100khz or 400khz 8-bit data 10- or 7-bit address slave transmitter and receiver master transmitter and receiver multiple bus masters supports ?ed v dd iic interface two independent 4 x 1 byte data buffers twelve memory-mapped, fully programmable con?uration registers one programmable interrupt request signal provides full management of all iic bus protocol programmable error recovery hdlcex interface multichannel hdlc controller core two full-duplex pulse code modulation (pcm) highway ports at speeds up to 8 mbps 32 transmit and 32 receive channels supports hdlc protocol as well as a transparent mode one channel per port, autonomous management of the i-frame and s-frame of the normal response mode (nrm) protocol software emulation of nrm mode
advance information powernp tm npe405l embedded processor data sheet 11 general purpose io (gpio) controller controller functions and gpio registers are programmed and accessed via memory-mapped opb bus master accesses most gpios are pin-shared with other functions. dcrs control whether a particular pin that has gpio capabilities acts as a gpio or is used for another purpose. the gpio function has 32 i/os. each gpio output is separately programmable to emulate an open-drain driver (drives to zero, three- stated if output bit is 1) universal interrupt controller (uic) two cascaded universal interrupt controllers (uics) provides the control, status, and communications necessary between the various sources of interrupts and the local powerpc processor. features include: supports 7 external and 29 internal interrupts edge triggered or level-sensitive positive or negative active non-critical or critical interrupt to ppc405 processor core programmable critical interrupt priority ordering programmable critical interrupt vector for faster vector processing 10/100 mbps ethernet mac two units capable of full- or half-duplex operation at up to 100mbps zmii bridge to external ethernet phys that support - reduced media independent interface (rmii) or serial media independent interface (smii) for multiple phy applications - media independent interface (mii) for single phy applications dedicated dma channel jtag ieee 1149.1 test access port ibm riscwatch debugger support jtag boundary scan description language (bsdl)
advance information powernp tm npe405l embedded processor data sheet 12 23mm, 324-ball e-pbga package top view bottom view 135 7 911131517 19 2 4 6 810 12 14 16 18 21 20 22 a b c d e f g h j k l m aa n p r t u v w y ab 23.0 23.0 1.0 1.0 note: all dimensions are in mm. thermal balls a1 corner 0.60 solder ball 2.65 max 0.60 nom
advance information powernp tm npe405l embedded processor data sheet 13 pin lists the following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. the page number listed gives the page in ?ignal functional description?on page 28 where the signals in the indicated interface group begin. signals listed alphabetically (part 1 of 8) signal name ball interface group page av dd h21 power 33 ba0 ba1 ab15 y14 sdram 29 banksel0 banksel1 banksel2 banksel3 aa07 y08 ab06 aa06 sdram 29 cas aa12 sdram 29 clken0 clken1 y13 aa13 sdram 29 [dmaack0 ]gpio13 [dmaack1 ]gpio14 [dmaack2 ]gpio15 [dmaack3 ]gpio16 u22 u21 t20 d17 external slave peripheral 30 [dmareq0 ]gpio9 [dmareq1 ]gpio10 [dmareq2 ]gpio11 [dmareq3 ]gpio12 p19 t22 t21 r20 external slave peripheral 30 dqm0 dqm1 dqm2 dqm3 u03 u01 r02 l01 sdram 29 dqmcb aa04 sdram 29 ecc0 ecc1 ecc2 ecc3 ecc4 ecc5 ecc6 ecc7 aa05 y06 ab04 aa03 y05 ab03 y04 w06 sdram 29 emc0mdclk ab16 ethernet 28 emc0mdio aa16 ethernet 28 [emc0sync]emc0txen[emc0tx0en] ab21 ethernet 28 emc0txd0[emc0tx0d0][emc0tx0d] emc0txd1[emc0tx0d1][emc0tx1d] emc0txd2[emc0tx1d0] emc0txd3[emc0tx1d1] aa22 u19 w20 y22 ethernet 28 emc0txen[emc0tx0en][emc0sync] ab21 ethernet 28 emc0txerr[emc0tx1en] ab20 ethernet 28 [emc0tx0en]emc0txen[emc0sync] ab21 ethernet 28
advance information powernp tm npe405l embedded processor data sheet 14 [emc0tx1en]emc0txerr ab20 ethernet 28 [eot0 ][tc0 ]gpio24 [eot1 ][tc1 ]gpio25 [eot2 ][tc2 ]gpio26 [eot3 ][tc3 ]gpio27 b19 b18 c16 b17 external slave peripheral 30 gnd a01 a05 a09 a14 a18 a22 b02 b21 c03 c20 d04 d08 d11 d12 d15 d19 e01 e22 h04 h19 j01 j09-j14 j22 k09-k14 l04 l09-l14 l19 m04 m09-m14 m19 n09-n14 p01 p09-p14 p22 r04 r19 v01 v22 w04 w08 w11 w12 w15 w19 y03 y20 power notes: 1. j09-j14, k09-k14, l09-l14, m09-m14, n09- n14, and p09-p14 are also thermal balls. 33 signals listed alphabetically (part 2 of 8) signal name ball interface group page
advance information powernp tm npe405l embedded processor data sheet 15 gnd aa02 aa21 ab01 ab05 ab09 ab14 ab18 ab22 power 33 gpio0[trcclk] b20 system 32 gpio1[ts1e] gpio2[ts2e] gpio3[ts1o] gpio4[ts2o] gpio5[ts3] gpio6[ts4] gpio7[ts5] gpio8[ts6] c18 a20 n20 n22 p21 p20 r22 r21 system 32 gpio9[dmareq0 ] gpio10[dmareq1 ] gpio11[dmareq2 ] gpio12[dmareq3 ] p19 t22 t21 r20 system 32 gpio13[dmaack0 ] gpio14[dmaack1 ] gpio15[dmaack2 ] gpio16[dmaack3 ] u22 u21 t20 d17 system 32 gpio17[irq0] gpio18[irq1] gpio19[irq2] gpio20[irq3] gpio21[irq4] gpio22[irq5] gpio23[irq6] f20 j20 l21 m21 aa17 ab17 w14 system 32 gpio24[eot0 ][tc0 ] gpio25[eot1 ][tc1 ] gpio26[eot2 ][tc2 ] gpio27[eot3 ][tc3 ] b19 b18 c16 b17 system 32 gpio28[uart1_dcd ][hdlcextxena] gpio29[uart1_ri ][hdlcextxenb] aa15 t01 system 32 gpio30 gpio31[perwe ] t03 a13 system 32 halt f22 system 32 hdlcexrxclk l20 hdlc 32-channel 28 hdlcexrxdataa hdlcexrxdatab m22 n21 hdlc 32-channel 28 hdlcexrxfs m20 hdlc 32-channel 28 hdlcextxclk k20 hdlc 32-channel 28 hdlcextxdataa hdlcextxdatab k21 l22 hdlc 32-channel 28 [hdlcextxena]gpio28[uart1_dcd ] [hdlcextxenb]gpio29[uart1_ri ] aa15 t01 hdlc 32-channel signals listed alphabetically (part 3 of 8) signal name ball interface group page
advance information powernp tm npe405l embedded processor data sheet 16 hdlcextxfs k22 hdlc 32-channe 28 iicscl[iecscl] iicsda[iecsda] c17 a19 internal peripheral 31 [irq0]gpio17 [irq1]gpio18 [irq2]gpio19 [irq3[gpio20 [irq4[gpio21 [irq5]gpio22 [irq6[gpio23 f20 j20 l21 m21 aa17 ab17 w14 interrupts 32 memaddr0 memaddr1 memaddr2 memaddr3 memaddr4 memaddr5 memaddr6 memaddr7 memaddr8 memaddr9 memaddr10 memaddr11 memaddr12 y12 y11 ab11 aa11 aa10 y10 ab10 aa09 y09 ab08 aa08 w09 ab07 sdram 29 memclkout0 memclkout1 aa14 ab13 sdram 29 signals listed alphabetically (part 4 of 8) signal name ball interface group page
advance information powernp tm npe405l embedded processor data sheet 17 memdata0 memdata1 memdata2 memdata3 memdata4 memdata5 memdata6 memdata7 memdata8 memdata9 memdata10 memdata11 memdata12 memdata13 memdata14 memdata15 memdata16 memdata17 memdata18 memdata19 memdata20 memdata21 memdata22 memdata23 memdata24 memdata25 memdata26 memdata27 memdata28 memdata29 memdata30 memdata31 ab02 aa01 u04 w03 y01 v03 y02 w01 w02 v02 u02 r03 t02 p04 r01 p03 p02 n01 n03 n02 m02 m01 m03 l03 l02 k02 k03 k01 j02 j03 h01 h02 sdram notes: 1. memdata00 is the most significant bit (msb). 2. memdata31 is the least significant bit (lsb) 29 ov dd d05 d07 d16 d18 e04 e19 g04 g19 t19 t04 v04 v19 w05 w07 w16 w18 power 33 signals listed alphabetically (part 5 of 8) signal name ball interface group page
advance information powernp tm npe405l embedded processor data sheet 18 peraddr4 peraddr5 peraddr6 peraddr7 peraddr8 peraddr9 peraddr10 peraddr11 peraddr12 peraddr13 peraddr14 peraddr15 peraddr16 peraddr17 peraddr18 peraddr19 peraddr20 peraddr21 peraddr22 peraddr23 peraddr24 peraddr25 peraddr26 peraddr27 peraddr28 peraddr29 peraddr30 peraddr31 d06 c04 a03 c05 b03 a04 c06 b04 b05 c07 b06 c08 b07 a07 d09 b08 a08 c09 b09 a10 c10 b10 b11 a11 c11 c12 a12 b12 external slave peripheral 30 perblast c15 external slave peripheral 30 perclk a17 external slave peripheral 30 percs0 percs1 percs2 percs3 b14 c14 a15 b15 external slave peripheral 30 perdata0 perdata1 perdata2 perdata3 perdata4 perdata5 perdata6 perdata7 perdata8 perdata9 perdata10 perdata11 perdata12 perdata13 perdata14 perdata15 j04 g01 g02 h03 f01 f02 g03 e02 d02 f03 d01 c02 e03 c01 d03 f04 external slave peripheral note: perdata00 is the most significant bit (msb) on this bus. 30 pererr j21 external slave peripheral 30 peroe d14 external slave peripheral 30 signals listed alphabetically (part 6 of 8) signal name ball interface group page
advance information powernp tm npe405l embedded processor data sheet 19 perpar0 perpar1 b01 a02 external slave peripheral 30 perr/w a16 external slave peripheral 30 perready b16 external slave peripheral 30 perwbe0 perwbe1 b13 c13 external slave peripheral 30 [perwe ]gpio31 a13 external slave peripheral 30 phy0col[phy0rx1er] w17 ethernet 28 phy0crs[phy0crs0dv] y18 ethernet 28 [phy0crs1dv]phy0rxdv y17 ethernet 28 phy0rxclk ab19 ethernet 28 [phy0refclk]phy0txclk y19 ethernet 28 phy0rxd0[phy0rx0d0][phy0rx0d] phy0rxd1[phy0rx0d1][phy0rx1d] phy0rxd2[phy0rx1d0] phy0rxd3[phy0rx1d1] y15 y16 aa18 aa19 ethernet 28 phy0rxdv[phy0crs1dv] y17 ethernet 28 phy0rxerr[phy0rx0er] aa20 ethernet 28 [phy0rx0er]phy0rxerr aa20 ethernet 28 phy0txclk[phy0refclk] y19 ethernet 28 ras ab12 sdram 29 reserved other 33 sysclk g22 system 32 syserr c21 system 32 sysreset a21 system 32 tck j19 jtag 32 [tc0 ][eot0 ]gpio24 [tc1 ][eot1 ]gpio25 [tc2 ][eot2 ]gpio26 [tc3 ][eot3 ]gpio27 b19 b18 c16 b17 external slave peripheral 30 tdi g21 jtag 32 tdo f21 jtag 32 testen h20 system 32 tmrclk d20 system 32 tms e21 jtag 32 [trcclk]gpio0 b20 trace 33 trst h22 jtag 32 [ts1e]gpio1 [ts2e]gpio2 [ts1o]gpio3 [ts2o]gpio4 [ts3]gpio5 [ts4]gpio6 [ts5]gpio7 [ts6]gpio8 c18 a20 n20 n22 p21 p20 r22 r21 trace 33 signals listed alphabetically (part 7 of 8) signal name ball interface group page
advance information powernp tm npe405l embedded processor data sheet 20 uart0_cts uart0_dcd uart0_dsr uart0_dtr uart0_ri uart0_rts uart0_rx uart0_tx b22 c19 a06 g20 d22 d21 c22 f19 internal peripheral 31 uart1_cts [uart1_dcd ]gpio28[hdlcextxena] uart1_dsr uart1_dtr [uart1_ri ]gpio29[hdlcextxenb] uart1_rts uart1_rx uart1_tx w22 aa15 w21 u20 t01 v21 v20 y21 internal peripheral 31 uartserclk e20 internal peripheral 31 v dd d10 d13 k19 k04 n19 n04 w10 w13 power 33 we y07 sdram 29 signals listed alphabetically (part 8 of 8) signal name ball interface group page
advance information powernp tm npe405l embedded processor data sheet 21 signals listed by ball assignment (part 1 of 6) ball signal name ball signal name ball signal name ball signal name a01 gnd b01 perpar0 c01 perdata13 d01 perdata10 a02 perpar1 b02 gnd c02 perdata11 d02 perdata8 a03 peraddr6 b03 peraddr8 c03 gnd d03 perdata14 a04 peraddr9 b04 peraddr11 c04 peraddr5 d04 gnd a05 gnd b05 peraddr12 c05 peradd7 d05 ov dd a06 uart0_dsr b06 peraddr14 c06 peraddr10 d06 peraddr4 a07 peraddr17 b07 peraddr16 c07 peraddr13 d07 ov dd a08 peraddr20 b08 peraddr19 c08 peraddr15 d08 gnd a09 gnd b09 peraddr22 c09 peraddr21 d09 peraddr18 a10 peraddr23 b10 peraddr25 c10 peraddr24 d10 v dd a11 peraddr27 b11 peraddr26 c11 peraddr28 d11 gnd a12 peraddr30 b12 peraddr31 c12 peraddr29 d12 gnd a13 gpio31[perwe ] b13 perwbe0 c13 perwbe1 d13 v dd a14 gnd b14 percs0 c14 percs1 d14 peroe a15 percs2 b15 percs3 c15 perblas d15 gnd a16 perr/w b16 perready c16 gpio26[eot2 ][tc2 ] d16 ov dd a17 perclk b17 gpio27[eot3 ][tc3 ] c17 iicscl[iecscl] d17 gpio16[dmaack3 ] a18 gnd b18 gpio25[eot1 ][tc1 ] c18 gpio1[ts1e] d18 ov dd a19 iicsda[iecsda] b19 gpio24[eot0 ][tc0 ] c19 uart0_dcd d19 gnd a20 gpio2[ts2e] b20 gpio0 c20 gnd d20 tmrclk a21 sysreset b21 gnd c21 syserr d21 uart0_rts a22 gnd b22 uart0_cts c22 uart0_rx d22 uart0_ri
advance information powernp tm npe405l embedded processor data sheet 22 e01 gnd f01 perdata4 g01 perdata1 h01 memdata30 e02 perdata7 f02 perdata5 g02 perdata2 h02 memdata31 e03 perdata12 f03 perdata9 g03 perdata6 h03 perdata3 e04 ov dd f04 perdata15 g04 ov dd h04 gnd e05 no ball f05 no ball g05 no ball h05 no ball e06 no ball f06 no ball g06 no ball h06 no ball e07 no ball f07 no ball g07 no ball h07 no ball e08 no ball f08 no ball g08 no ball h08 no ball e09 no ball f09 no ball g09 no ball h09 no ball e10 no ball f10 no ball g10 no ball h10 no ball e11 no ball f11 no ball g11 no ball h11 no ball e12 no ball f12 no ball g12 no ball h12 no ball e13 no ball f13 no ball g13 no ball h13 no ball e14 no ball f14 no ball g14 no ball h14 no ball e15 no ball f15 no ball g15 no ball h15 no ball e16 no ball f16 no ball g16 no ball h16 no ball e17 no ball f17 no ball g17 no ball h17 no ball e18 no ball f18 no ball g18 no ball h18 no ball e19 ov dd f19 uart0_tx g19 ov dd h19 gnd e20 uartserclk f20 gpio17[irq0] g20 uart0_dtr h20 testen e21 tms f21 tdo g21 tdi h21 av dd e22 gnd f22 halt g22 sysclk h22 trst signals listed by ball assignment (part 2 of 6) ball signal name ball signal name ball signal name ball signal name
advance information powernp tm npe405l embedded processor data sheet 23 j01 gnd k01 memdata27 l01 dqm3 m01 memdata21 j02 memdata28 k02 memdata25 l02 memdata24 m02 memdata20 j03 memdata29 k03 memdata26 l03 memdata23 m03 memdata22 j04 perdata0 k04 v dd l04 gnd m04 gnd j05 k05 no ball l05 no ball m05 no ball j06 k06 no ball l06 no ball m06 no ball j07 k07 no ball l07 no ball m07 no ball j08 k08 no ball l08 no ball m08 no ball j09 gnd k09 gnd l09 gnd m09 gnd j10 gnd k10 gnd l10 gnd m10 gnd j11 gnd k11 gnd l11 gnd m11 gnd j12 gnd k12 gnd l12 gnd m12 gnd j13 gnd k13 gnd l13 gnd m13 gnd j14 gnd k14 gnd l14 gnd m14 gnd j15 k15 no ball l15 no ball m15 no ball j16 k16 no ball l16 no ball m16 no ball j17 k17 no ball l17 no ball m17 no ball j18 k18 no ball l18 no ball m18 no ball j19 tck k19 v dd l19 gnd m19 gnd j20 gpio18[irq1] k20 hdlcextxclk l20 hdlcexrxclk m20 hdlcexrxfs j21 pererr k21 hdlcextxdataa l21 gpio19[irq2] m21 gpio20[irq3] j22 gnd k22 hdlcextxfs l22 hdlcextxdatab m22 hdlcexrxdataa signals listed by ball assignment (part 3 of 6) ball signal name ball signal name ball signal name ball signal name
advance information powernp tm npe405l embedded processor data sheet 24 n01 memdata17 p01 gnd r01 memdata14 t01 gpio29[uart1_ri ] [hdlcextxenb] n02 memdata19 p02 memdata16 r02 dqm2 t02 memdata12 n03 memdata18 p03 memdata15 r03 memdata11 t03 gpio30 n04 v dd p04 memdata13 r04 gnd t04 ov dd n05 no ball p05 no ball r05 no ball t05 no ball n06 no ball p06 no ball r06 no ball t06 no ball n07 no ball p07 no ball r07 no ball t07 no ball n08 no ball p08 no ball r08 no ball t08 no ball n09 gnd p09 gnd r09 no ball t09 no ball n10 gnd p10 gnd r10 no ball t10 no ball n11 gnd p11 gnd r11 no ball t11 no ball n12 gnd p12 gnd r12 no ball t12 no ball n13 gnd p13 gnd r13 no ball t13 no ball n14 gnd p14 gnd r14 no ball t14 no ball n15 no ball p15 no ball r15 no ball t15 no ball n16 no ball p16 no ball r16 no ball t16 no ball n17 no ball p17 no ball r17 no ball t17 no ball n18 no ball p18 no ball r18 no ball t18 no ball n19 v dd p19 gpio9[dmareq0 ] r19 gnd t19 ov dd n20 gpio3[ts1o] p20 gpio6[ts4] r20 gpio12[dmareq3 ] t20 gpio15[dmaack2 ] n21 hdlcexrxdatab p21 gpio5[ts3] r21 gpio8[ts6] t21 gpio11[dmareq2 ] n22 gpio4[ts2o] p22 gnd r22 gpio7[ts5] t22 gpio10[dmareq1 ] signals listed by ball assignment (part 4 of 6) ball signal name ball signal name ball signal name ball signal name
advance information powernp tm npe405l embedded processor data sheet 25 u01 dqm1 v01 gnd w01 memdata7 y01 memdata4 u02 memdata10 v02 memdata9 w02 memdata8 y02 memdata6 u03 dqm0 v03 memdata5 w03 memdata3 y03 gnd u04 memdata2 v04 ov dd w04 gnd y04 ecc6 u05 no ball v05 no ball w05 ov dd y05 ecc4 u06 no ball v06 no ball w06 ecc7 y06 ecc1 u07 no ball v07 no ball w07 ov dd y07 we u08 no ball v08 no ball w08 gnd y08 banksel1 u09 no ball v09 no ball w09 memaddr11 y09 memaddr8 u10 no ball v10 no ball w10 v dd y10 memaddr5 u11 no ball v11 no ball w11 gnd y11 memaddr1 u12 no ball v12 no ball w12 gnd y12 memaddr0 u13 no ball v13 no ball w13 v dd y13 clken0 u14 no ball v14 no ball w14 gpio23[irq6] y14 ba1 u15 no ball v15 no ball w15 gnd y15 phy0rxd0 [phy0rx0d0] [phy0rx0d] u16 no ball v16 no ball w16 ov dd y16 phyrxd1 [phy0rx0d1] [phy0rx1d] u17 no ball v17 no ball w17 phy0col[phy0rx1er] y17 phy0rxdv [phy0crs1dv] u18 no ball v18 no ball w18 ov dd y18 phy0crs [phy0crs0dv] u19 emc0txd1 [emc0tx0d1] [emc0tx1d] v19 ov dd w19 gnd y19 phy0txclk [phy0refclk] u20 uart1_dtr v20 uart1_rx w20 emc0txd2 [emc0tx1d0] y20 gnd u21 gpio14[dmaack1 ] v21 uart1_rts w21 uart1_dsr y21 uart1_tx u22 gpio13[dmaack0 ] v22 gnd w22 uart1_cts y22 emc0txd3 [emc0tx1d1] signals listed by ball assignment (part 5 of 6) ball signal name ball signal name ball signal name ball signal name
advance information powernp tm npe405l embedded processor data sheet 26 aa01 memdata1 ab01 gnd aa02 gnd ab02 memdata0 aa03 ecc3 ab03 ecc5 aa04 dqmcb ab04 ecc2 aa05 ecc0 ab05 gnd aa06 banksel3 ab06 banksel2 aa07 banksel0 ab07 memaddr12 aa08 memaddr10 ab08 memaddr9 aa09 memaddr7 ab09 gnd aa10 memaddr4 ab10 memaddr6 aa11 memaddr3 ab11 memaddr2 aa12 cas ab12 ras aa13 clken1 ab13 memclkout1 aa14 memclkout0 ab14 gnd aa15 gpio28[uart1_dcd ] [hdlcextxena] ab15 ba0 aa16 emc0mdio ab16 emc0mdclk aa17 gpio21[irq4] ab17 gpio22[irq5] aa18 phy0rxd2 [phy0rx1d0] ab18 gnd aa19 phy0rxd3 [phy0rx1d1] ab19 phy0rxclk aa20 phy0rxerr [phy0rx0er] ab20 emc0txerr [emc0tx1en] aa21 gnd ab21 emc0txen [emc0tx0en] [emc0sync] aa22 emc0txd0 [emc0tx0d0] [emc0tx0d] ab22 gnd signals listed by ball assignment (part 6 of 6) ball signal name ball signal name ball signal name ball signal name
advance information powernp tm npe405l embedded processor data sheet 27 signal list the table following table provides a summary of the number of package pins associated with each functional interface group. in the table ?ignal functional description?on page 28, each external signal is listed along with a short description of the signal function. the signals are grouped together according to their function. some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. in most cases, the signal name is shown in this table without any multiplexed signal names that may be associated with it. in cases where multiplexed signals are in the same functional group, the names appear as a default signal followed by secondary signals in square brackets (for example, pcic0:3[be0:3 ]). active-low signals such as be0:3 are marked with an overline. any signal that is not the primary (default) signal on a multiplexed pin is shown in square backets. the active signal on a multiplexed pin is controlled by programming. it is expected that in any single application, a particular pin will always be programmed to serve the same function. the flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. in addition to multiplexing, many pins are also multi-purpose. for example, emc0txerr[emc0tx1en] functions as an error output when the ethernet interface operates in mii mode, or as a transmit enable output when operating in rmii mode. one group of pins is used as strapped inputs during system reset. these pins function as strapped inputs only during reset and are used for other functions during normal operation (see ?nitialization?on page 47). note that these are not multiplexed pins since the function of the pins is not programmable. the following table lists all of the i/o signals provided by the npe405l. please refer to ?ignals listed alphabetically?on page 13 for the pin number to which each signal is assigned. pin summary group no. of pins nonmultiplexed signals 167 multiplexed signals 48 total signal pins 215 av dd 1 ov dd 16 v dd 8 gnd 48 thermal (and gnd) 36 reserved 0 total pins 324
advance information powernp tm npe405l embedded processor data sheet 28 signal functional description (part 1 of 6) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes hdlcex interface hdlcextxclk transmit clock i 3.3v lvttl hdlcextxfs transmit frame synchronization i 3.3v lvttl hdlcextxdataa transmit data port a o 3.3v lvttl hdlcextxdatab transmit data port b o 3.3v lvttl hdlcexrxclk receive clock i 3.3v lvttl hdlcexrxfs receive frame synchronization i 3.3v lvttl hdlcexrxdataa receive data port a i 3.3v lvttl hdlcexrxdatab receive data port b i 3.3v lvttl [hdlcextxena] transmit enable port a o 5v tolerant 3.3v lvttl [hdlcextxenb] transmit enable port b o 5v tolerant 3.3v lvttl ethernet interface emc0mdclk management data clock. the mdclk is sourced to the phy. management information is transferred synchronously with respect to this clock (mii, rmii, and smii). o 5v tolerant 3.3v lvttl emc0mdio management data input/output is a bidirectional signal between the ethernet controller and the phy. it is used to transfer control and status information (mii, rmii, and smii). i/o 5v tolerant 3.3v lvttl 1, 4 emc0txd0[emc0tx0d0][emc0tx0d] emc0txd1[emc0tx0d1][emc0tx1d] emc0txd2[emc0tx1d0] emc0txd3[emc0tx1d1] transmit data. a nibble wide data bus towards the net. the data is synchronous with phy0txclk (mii 0[rmii 0 and 1][smii 0, 1, 2, and 3]). o 3.3v lvttl emc0txen[emc0tx0en][emc0sync] transmit enable. this signal is driven by emac2 to the phy. data is valid during the active state of this signal. deassertion of this signal indicates end of frame transmission. this signal is synchronous with phytxclk (mii 0[rmii 0]). or smii sync. o 3.3v lvttl emc0txerr[emc0tx1en] transmit error. this signal is generated by the ethernet controller, is connected to the phy and is synchronous with the phy0txclk. it informs the phy that an error was detected (mii 0). or transmit enable [rmii 1]. o 5v tolerant 3.3v lvttl
advance information powernp tm npe405l embedded processor data sheet 29 phy0col[phy0rx1er]l collision [receive error] signal from the phy. this is an asynchronous signal (mii 0). or receive error ([rmii 1]). i 5v tolerant 3.3v lvttl phy0crs[phy0crs0dv] carrier sense signal from the phy. this is an asynchronous signal (mii 0). or carrier sense data valid ([rmii 0]). i 5v tolerant 3.3v lvttl 1, 5 phy0rxclk receiver medium clock. this signal is generated by the phy (mii 0). i 5v tolerant 3.3v lvttl 1, 4 phy0rxd0[phy0rx0d0][phy0rx0d] phy0rxd1[phy0rx0d1][phy0rx1d] phy0rxd2[phy0rx1d0] phy0rxd3[phy0rx1d1] received data. this is a nibble wide bus from the phy. the data is synchronous with phy0rxclk (mii 0[rmii 0 and 1][smii 0, 1, 2, and 3]). i 5v tolerant 3.3v lvttl 1, 4 phy0rxdv[phy0crs1dv] receive data valid. data on the data bus is valid when this signal is activated. deassertion of this signal indicates end of the frame reception (mii 0). or carrier sense data valid ([rmii 1]) i 5v tolerant 3.3v lvttl 1, 5 phy0rxerr[phy0rx0er] receive error. this signal comes from the phy and is synchronous with phy0rxclk (mii 0 [rmii 0]). i 5v tolerant 3.3v lvttl 1, 5 phy0txclk[phy0refclk] transmit medium clock. this signal is generated the phy ([mii 0]). or reference clock [rmii and smii]. i 5v tolerant 3v lvttl 1, 4 sdram interface memdata0:31 memory data bus notes: 1. memdata0 is the most significant bit (msb). 2. memdata31 is the least significant bit (lsb). i/o 3.3v lvttl 4 memaddr12:0 memory address bus. notes: 1. memaddr12 is the most significant bit (msb). 2. memaddr0 is the least significant bit (lsb). o 3.3v lvttl ba1:0 bank address supporting up to 4 internal banks o 3.3v lvttl ras row address strobe. o 3.3v lvttl cas column address strobe. o 3.3v lvttl dqm0:3 dqm for byte lanes 0 (memdata0:7), 1 (memdata8:15), 2 (memdata16:23), and 3 (memdata24:31) o 3.3v lvttl dqmcb dqm for ecc check bits. o 3.3v lvttl ecc0:7 ecc check bits 0:7. i/o 3.3v lvttl 4 signal functional description (part 2 of 6) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes
advance information powernp tm npe405l embedded processor data sheet 30 banksel0:3 select up to four external sdram banks. o 3.3v lvttl we write enable. o 3.3v lvttl clken0:1 sdram clock enable. o 3.3v lvttl memclkout0:1 two copies of an sdram clock allows, in some cases, glueless sdram attachment without requiring this signal to be repowered by a pll or zero-delay buffer. o 3.3v lvttl external slave peripheral interface perdata0:15 peripheral data bus used by npe405l. note: perdata00 is the most significant bit (msb) on this bus. i/o 5v tolerant 3.3v lvttl 1 peraddr4:31 peripheral address bus used by npe405l. o 5v tolerant 3.3v lvttl perpar0:1 peripheral byte parity signals. i/o 5v tolerant 3.3v lvttl 1 perwbe0: 1 as outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. as outputs, pins are used by either peripheral controller or dma controller depending upon the type of transfer involved. o 5v tolerant 3.3v lvttl 2 perwe peripheral write enable. low when any of the two perwbe signals are low. i/o 5v tolerant 3.3v lvttl [percs0: 3 ] peripheral chip selects o 5v tolerant 3.3v lvttl 2 peroe used by either peripheral controller or dma controller depending upon the type of transfer involved. when the npe405l is the bus master, it enables the selected sdrams to drive the bus. o 5v tolerant 3.3v lvttl 2 perr/w used by the npe405l as an output by either the peripheral controller or dma controller depending upon the type of transfer involved. high indicates a read from memory, low indicates a write to memory. o 5v tolerant 3.3v lvttl perready used by a peripheral slave to indicate it is ready to transfer data. i 5v tolerant 3.3v lvttl 1 perblast used by the npe405l to indicate the last transfer of a memory access. o 5v tolerant 3.3v lvttl 4 perclk peripheral clock to be used by synchronous peripheral slaves. o 5v tolerant 3.3v lvttl pererr used as an input to record external slave peripheral errors. i 5v tolerant 3.3v lvttl 1, 5 [dmareq0:3 ] used by slave peripherals to indicate they are prepared to transfer data. i 5v tolerant 3.3v lvttl 1, 5 signal functional description (part 3 of 6) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes
advance information powernp tm npe405l embedded processor data sheet 31 [dmaack0:3 ] used by the npe405l to indicate that data transfers have occurred. o 5v tolerant 3.3v lvttl [eot0:3 ][tc0:3 ] end of transfer[terminal count]. i/o 5v tolerant 3.3v lvttl 1, 5 internal peripheral interface uartserclk serial clock used to provide an alternative clock to the internally generated serial clock. used in cases where the allowable internally generated baud rates are not satisfactory. this input can be individually connected to either or both uart0 and uart1. i 5v tolerant 3.3v lvttl 1, 4 uart0_rx uart0 receive data. i 5v tolerant 3.3v lvttl 1, 4 uart0_tx uart0 transmit data. o 5v tolerant 3.3v lvttl [uart0_dcd ] uart0 data carrier detect. i 5v tolerant 3.3v lvttl 1, 4 [uart0_dsr ] uart0 data set ready. i 5v tolerant 3.3v lvttl 1, 4 [uart0_cts ] uart0 clear to send. i 5v tolerant 3.3v lvttl 1, 4 [uart0_dtr ] uart0 data terminal ready. o 5v tolerant 3.3v lvttl [uart0_rts ] uart0 request to send. o 5v tolerant 3.3v lvttl [uart0_ri ] uart0 ring indicator. i 5v tolerant 3.3v lvttl r 1, 4 uart1_rx uart1 receive data. i 5v tolerant 3.3v lvttl 1, 4 uart1_tx uart1 transmit data. o 5v tolerant 3.3v lvttl [uart1_dcd ] uart1 data carrier detect. i 5v tolerant 3.3v lvttl 1, 4 [uart1_dsr ] uart1 data set ready. i 5v tolerant 3.3v lvttl 1, 4 [uart1_cts ] uart1 clear to send. i 5v tolerant 3.3v lvttl 1, 4 [uart1_dtr ] uart1 data terminal ready. o 5v tolerant 3.3v lvttl 6 [uart1_rts ] uart1 request to send. o 5v tolerant 3.3v lvttl 6 [uart1_ri ] uart1 ring indicator. i 5v tolerant 3.3v lvttl 1, 4 signal functional description (part 4 of 6) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes
advance information powernp tm npe405l embedded processor data sheet 32 iicscl iic serial clock. i/o 5v tolerant 3.3v lvttl 1, 2 iicsda iic serial data. i/o 5v tolerant 3.3v lvttl 1, 2 interrupts interface [irq0:6] interrupt requests. i 5v tolerant 3.3v lvttl 1, 5 jtag interface tdi test data in. i 5v tolerant 3.3v lvttl 1, 4 tms test mode select. i 5v tolerant 3.3v lvttl 1, 4 tdo test data out. o 5v tolerant 3.3v lvttl tck test clock. i 5v tolerant 3.3v lvttl 1, 4 trst test reset. i 5v tolerant 3.3v lvttl 2, 5 system interface sysclk main system clock input. i 3.3v analog wire w/esd sysreset main system reset. i/o 5v tolerant 3.3v lvttl 1, 2 syserr set to 1 when a machine check is generated. o 5v tolerant 3.3v lvttl halt halt from external debugger. i 5v tolerant 3.3v lvttl 1, 4 gpio0 general purpose i/o. to access this function, software must toggle a dcr bit. i/o 5v tolerant 3.3v lvttl 1, 6 gpio1:31 general purpose i/o. to access this function, software must toggle a dcr bit. i/o 5v tolerant 3.3v lvttl 1 testen test enable. used only for manufacturing tests. pull down for normal operation. i 3.3v lvttl rcvr w/ pd 3 tmrclk this input must toggle at a rate of less than one half the cpu core frequency (less than 100mhz in most cases). in most cases this input toggles much slower (in the 1mhz to 10mhz range). i 5v tolerant 3.3v lvttl 1, 4 signal functional description (part 5 of 6) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes
advance information powernp tm npe405l embedded processor data sheet 33 trace interface [ts1e] [ts2e] even trace execution status.to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl [ts1o] [ts2o] odd trace execution status. to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl [ts3:6] trace status. to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl [trcclk] trace interface clock. a toggling signal that is always half of the cpu core frequency. to access this function, software must toggle a dcr bit. o 5v tolerant 3.3v lvttl 1, 6 power pins gnd ground note: j09-j14, k09-k14, l09-l14, m09-m14, n09-n14, and p09-p14 are also thermal balls. i hardwire v dd logic voltage?.5v i hardwire ov dd output driver voltage?.3v i hardwire av dd filtered pll voltage?.5v i 3.3v dc wire w/esd other pins reserved do not connect signals, voltage, or ground to these pins. n/a n/a signal functional description (part 6 of 6) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v, 10k ? to 5v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during reset; pull-up or pull-down required signal name description i/o type notes
advance information powernp tm npe405l embedded processor data sheet 34 notes: 1. for a chip mounted on a jedec 2s2p card without a heat sink. 2. for a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. case temperature, t c , is measured at top center of case surface with device soldered to circuit board. b. t a = t c ?p ca , where t a is ambient temperature and p is power consumption. c. t cmax = t jmax ?p jc , where t jmax is maximum junction temperature and p is power consumption. absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or beyond these maximum ratings can cause permanent damage to the device. characteristic symbol value unit supply voltage (internal logic) v dd 0 to 2.7 v supply voltage (i/o interface) ov dd 0 to 3.6 v pll supply voltage av dd 0 to 2.7 v input voltage (3.3v lvttl receivers) v in 0 to 3.6 v input voltage (5.0v lvttl receivers) v in 0 to 5.5 v storage temperature range t stg -55 to 150 c case temperature under bias t c -40 to +120 c package thermal speci?ations the npe405l is designed to operate within a case temperature range of -40?c to 120?c. thermal resistance values for the e-pbga packages in a convection environment are as follows: package?hermal resistance symbol air?w ft/min (m/sec) unit 0 (0) 100 (0.51) 200 (1.02) 23mm, 324-balls?unction-to-case jc ?/w 23mm, 324-balls?ase-to-ambient 1 ca ?/w
advance information powernp tm npe405l embedded processor data sheet 35 recommended dc operating conditions device operation beyond the conditions speci?d is not recommended. extended operation beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes logic supply voltage v dd 2.3 2.5 2.7 v i/o supply voltage ov dd 3.0 3.3 3.6 v pll supply voltage av dd 2.3 2.5 2.7 v input logic high (3.3v lvttl receivers) v ih 2.0 ov dd v input logic high (5.0v lvttl receivers) v ih 2.0 5.5 v input logic low v il 0 0.8 v output logic high v oh 2.4 ov dd v output logic low v ol 0 0.4 v input leakage current (no pull-up or pull-down) i il1 00 a input leakage current for pull- down i il2 0 (lpdl) 400 (mpul) a input leakage current for pull-up i il3 ? 250 (lpdl) 0 (mpul) a input max allowable overshoot (3.3v lvttl receivers) v imao3 ov dd + 0.6 v input max allowable overshoot (5.0v lvttl receivers) v imao5 5.5 v input max allowable undershoot (3.3v or 5.0v receivers) v imau ? 0.6 v output max allowable overshoot (3.3v or 5.0v receivers) v omao ov dd + 0.3 v output max allowable undershoot (3.3v and 5.0v receivers) v omau3 ? 0.6 v case temperature t c ? 40 85 c
advance information powernp tm npe405l embedded processor data sheet 36 test conditions clock timing and switching characteristics are specified in accordance with operating conditions shown in the table ?ecommended dc operating conditions.?ac specifications are characterized at v dd = 3.14v and t j = 100?c with the 50pf test load (c l ) shown in the figure at right. capacitance parameter symbol maximum unit notes input capacitance group 1 (3.3v lvttl //o) c in1 2.5 pf input capacitance group 2 (5v tolerant lvttl i/o) c in2 3.5 pf input capacitance group 1 (rx only pins) c in4 0.75 pf dc electrical characteristics parameter symbol minimum typical maximum unit active operating current (v dd )i dd 390 600 ma active operating current (ov dd )i odd 35 100 ma pll voltage (av dd )v pll 2.3 2.5 2.7 v pll v dd input current i pll 16 23 ma output pin c l c l = 50pf for all signals
advance information powernp tm npe405l embedded processor data sheet 37 timing waveform sysclk and memclk timing symbol parameter min max units sysclk input f c sysclk clock input frequency 25 66.6 mhz t c sysclk clock period 15 40 ns t cs clock edge stability 0.15 ns t ch clock input high time 40% of nominal period 60% of nominal period ns t cl clock input low time 40% of nominal period 60% of nominal period ns note: input slew rate > 2v/ns memclk output f c memclk clock output frequency?00mhz 100 mhz t c memclk clock period?00mhz 10 ns f c memclk clock output frequency?66mhz 133 mhz t c memclk clock period?66mhz 7.5 ns t ch clock output high time 35% of nominal period 65% of nominal period ns t cl clock output low time 35% of nominal period 65% of nominal period ns t cl t ch t c 2.0v 1.5v 0.8v
advance information powernp tm npe405l embedded processor data sheet 38 spread spectrum clocking care must be taken when using a spread spectrum clock generator (sscg) with the npe405l. this controller uses a pll for clock generation inside the chip. the accuracy with which the pll follows the sscg is referred to as tracking skew. the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the npe405l the following conditions must be met: the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the npe405l with one or more internal clocks at their maximum supported frequency, the sscg can only lower the frequency. the maximum frequency deviation cannot exceed ? 3%, and the modulation frequency cannot exceed 40khz. in some cases, on-board npe405l peripherals impose more stringent requirements (see note 1). use the peripheral bus clock for logic that is synchronous to the peripheral bus since this clock tracks the modulation. use the sdram memclk since it also tracks the modulation. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is running at precise baud rates. if an external serial clock is used the baud rate is unaffected by the modulation 2. ethernet operation is unaffected. 3. iic operation is unaffected. caution: it is up to the system designer to ensure that any sscg used with the npe405l meets the above requirements and does not adversely affect other aspects of the system.
advance information powernp tm npe405l embedded processor data sheet 39 peripheral interface clock timings parameter min max units emc0mdclk output frequency 2.5 mhz emc0mdclk period 400 ns emc0mdclk output high time 160 ns emc0mdclk output low time 160 ns phy0txclk input frequency 2.5 25 mhz phy0txclk period 40 400 ns phy0txclk input high time 35% of nominal period ns phy0txclk input low time 35% of nominal period ns phy0rxclk input frequency 2.5 25 mhz phy0rxclk period 40 400 ns phy0rxclk input high time 35% of nominal period ns phy0rxclk input low time 35% of nominal period ns perclk output frequency?00mhz (for synchronous slaves) 50 mhz perclk period?00mhz 20 ns perclk output frequency?66mhz (for synchronous slaves) 66 perclk period?66mhz 15 perclk output high time 50% of nominal period 66% of nominal period ns perclk output low time 33% of nominal period 50% of nominal period ns uartserclk input frequency (note 1) 1000/(2t opb +2ns) mhz uartserclk period 2t opb +2 ?s uartserclk input high time t opb +1 ?s uartserclk input low time t opb +1 ?s tmrclk input frequency?00mhz 50 mhz tmrclk period?00mhz 20 ns tmrclk input frequency?66mhz 66 tmrclk period?66mhz 15 tmrclk input high time 40% of nominal period 60% of nominal period ns tmrclk input low time 40% of nominal period 60% of nominal period ns notes: 1. t opb is the period in ns of the opb clock. the internal opb clock runs at 1/2 the frequency of the plb clock. the maximum opb clock frequency is 50 mhz for 200mhz parts and 66mhz.for 266mhz parts.
advance information powernp tm npe405l embedded processor data sheet 40 input setup and hold waveform output delay and float timing waveform 1.5v sysclk 1.5v t is t ih min min inputs valid data bus (inputs) d0:31 min min t ih t is 1.5v valid valid valid t ov t oh 1.5v min outputs sysclk outputs t of min max max 1.5v 1.5v
advance information powernp tm npe405l embedded processor data sheet 41 i/o speci?ations?00mhz (part 1 of 3) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) ethernet interface emc0mdclk n/a n/a 7.4 1.5 12 8 1, async emc0mdio n/a n/a 8.8 1.2 12 8 emc0mdclk 1 emc0txd0:3 [emc0tx0:1d0:1 [emc0tx0:1d] n/a n/a 10.5 [7.3] [5.0] 3.0 [2.3] [1.7] 12 8 phytx 1 emc0txen [emc0tx0en] [emc0sync] n/a n/a 11.8 [7.2] [5.6] 2.9 [2.3] [1.7] 12 8 phytx 1 emc0txerr [emc0tx1en] n/a n/a 11.8[7.4] 2.9[2.4] 12 8 phytx 1 phy0col[phy0rx1er]l async[0.2] async[1.7] n/a n/a n/a n/a 1 phy0crs[phy0crs0dv] async[0.1] async[1.9] n/a n/a n/a n/a 1 phy0rxclk n/a n/a n/a n/a n/a n/a 1, async phy0rxd0:3 [phy0rx0:1d0:1] [phy0rx0:1d] 1.5 [0.8] [0.9] 1.7 [1.7] [0.3] n/a n/a n/a n/a phyrx 1 phy0rxdv [phy0crs1dv] 1.3[0.7] 1.7[1.7] n/a n/a n/a n/a phyrx 1 phy0rxerr[phy0rx0er] 1.3[0.7] 1.8[1.9] n/a n/a n/a n/a phyrx 1 phy0txclk[phy0refclk] n/a n/a n/a n/a n/a n/a 1, async hdlcex interface hdlcexrxclk n/a n/a n/a n/a n/a n/a hdlcexrxdataa:b 23.8 2.1 n/a n/a n/a n/a hdlcexrxfs 24.2 1.1 n/a n/a n/a n/a hdlcextxclk n/a n/a n/a n/a n/a n/a hdlcextxdataa:b n/a n/a 10.5 3.3 12 8 hdlcextxfs 20.3 1.0 n/a n/a n/a n/a hdlcextxena [gpio28][uart1_dcd ] n/a n/a 11.3 3.5 12 8 hdlcextxenb [gpio29][uart1_ri ] n/a n/a 11.8 3.8 12 8 internal peripheral interface iicscl async async async async 17 11 iicsda async async async async 17 11 [uart0_cts ] async async n/a n/a n/a n/a [uart0_dcd ] async async n/a n/a n/a n/a
advance information powernp tm npe405l embedded processor data sheet 42 [uart0_dsr ] async async n/a n/a n/a n/a [uart0_dtr ] n/a n/a async async 12 8 [uart0_ri ] async async n/a n/a n/a n/a [uart0_rts ] n/a n/a async async 12 8 uart0_rx async async n/a n/a n/a n/a uart0_tx n/a n/a async async 12 8 [uart1_cts ] async async n/a n/a n/a n/a [uart1_dcd ]gpio28 [hdlcextxena] async async n/a n/a n/a n/a [uart1_dsr ] async async n/a n/a n/a n/a [uart1_dtr ] n/a n/a async async 12 8 [uart1_ri ]gpio29 [hdlcextxenb] async async n/a n/a n/a n/a [uart1_rts ] n/a n/a async async 12 8 uart1_rx async async n/a n/a n/a n/a uart1_tx n/a n/a async async 12 8 uartserclk async async n/a n/a n/a n/a interrupts interface [irq0:6]gpio17:23 async async n/a n/a n/a n/a jtag interface tck async async n/a n/a n/a n/a tdi async async n/a n/a n/a n/a tdo n/a n/a async async 12 8 tms async async n/a n/a n/a n/a trst async async n/a n/a n/a n/a system interface [trcclk]gpio0 n/a n/a 11.2 1.2 12 8 [ts1e]gpio1 n/a n/a 7.0 1.2 12 8 [ts2e]gpio2 n/a n/a 7.0 1.2 12 8 [ts1o]gpio3 n/a n/a 6.5 1.0 12 8 [ts2o]gpio4 n/a n/a 6.4 1.0 12 8 [ts3]gpio5 n/a n/a 6.4 1.0 12 8 [ts4]gpio6 n/a n/a 6.4 1.0 12 8 [ts5]gpio7 n/a n/a 6.6 1.0 12 8 [ts6]gpio8 n/a n/a 6.4 1.0 12 8 gpio30 async async async async 12 8 halt async async n/a n/a n/a n/a i/o speci?ations?00mhz (part 2 of 3) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum)
advance information powernp tm npe405l embedded processor data sheet 43 sysclk n/a n/a n/a n/a n/a n/a syserr n/a n/a 5.3 1.7 12 8 sysreset n/a n/a n/a n/a 12 8 testen dc dc n/a n/a n/a n/a tmrclk n/a n/a async async n/a n/a sdram interface ba1:0 n/a n/a 7.2 1.5 19 12 sysclk 2, 3 banksel3:0 n/a n/a 5.8 1.0 19 12 sysclk 3 cas n/a n/a 7.0 1.4 19 12 sysclk 2, 3 clken0:1 n/a n/a 4.9 1.0 40 25 sysclk 3 dqm3:0 n/a n/a 5.9 1.0 19 12 sysclk 3 dqmcb n/a n/a 5.9 1.0 19 12 sysclk 3 ecc7:0 2.0 0.3 5.7 1.0 19 12 sysclk 3 memaddr12:0 n/a n/a 7.2 1.4 19 12 sysclk 2, 3 memclkout0:1 n/a n/a 0.4 -1.2 19 12 sysclk 3, 4 memdata31:0 2.0 0.3 5.6 1.0 19 12 sysclk 3 ras n/a n/a 7.4 1.6 19 12 sysclk 2, 3 we n/a n/a 7.1 1.4 19 12 sysclk 2, 3 external slave peripheral interface dmareq0:3 [gpio9:12] 4.8 0.0 7.0 1.1 n/a n/a perclk dmaack0:3 [gpio13:16] n/a n/a 7.5 1.1 12 8 perclk eot0:3 [tc0:3 ] [gpio24:27] 4.3 -0.1 8.5 1.2 12 8 perclk peraddr4:31 n/a n/a 8.5 0.9 17 11 perclk perblast n/a n/a 7.4 1.4 12 8 perclk percs0: 3 n/a n/a 7.2 1.3 12 8 perclk perdata0:15 4.8 1.0 9.3 1.0 17 11 perclk peroe n/a n/a 7.6 1.4 12 8 perclk perpar0:1 3.1 0.0 8.3 0.9 17 11 perclk perr/w n/a n/a 7.5 1.4 12 8 perclk perready 7.5 -0.5 n/a n/a n/a n/a perclk perwbe0: 1 n/a n/a 7.5 1.3 12 8 perclk perclk n/a n/a 0.5 -0.9 17 11 plb clk 5 pererr 4.0 -0.6 n/a n/a n/a n/a perclk perwe [gpio31] n/a n/a 8.3 1.3 12 8 i/o speci?ations?00mhz (part 3 of 3) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum)
advance information powernp tm npe405l embedded processor data sheet 44 i/o speci?ations?66mhz (part 1 of 3) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum) ethernet interface emc0mdclk n/a n/a 7.4 1.5 12 8 1, async emc0mdio n/a n/a 6.7 1.2 12 8 emc0mdclk 1 emc0txd0:3 [emc0tx0:1d0:1 [emc0tx0:1d] n/a n/a 7.7 [5.6] [4.6] 3.0 [2.3] [1.7] 12 8 phytx 1 emc0txen [emc0tx0en] [emc0sync] n/a n/a 9.4 [5.5] [4.2] 2.9 [2.3] [1.7] 12 8 phytx 1 emc0txerr [emc0tx1en] n/a n/a 9.4[5.7] 2.9[2.4] 12 8 phytx 1 phy0col[phy0rx1er]l async[0.1] async[1.4] n/a n/a n/a n/a 1 phy0crs[phy0crs0dv] async[0.1] async[1.5] n/a n/a n/a n/a 1 phy0rxclk n/a n/a n/a n/a n/a n/a 1, async phy0rxd0:3 [phy0rx0:1d0:1] [phy0rx0:1d] 1.5 [0.8] [0.8] 1.4 [1.3] [0.2] n/a n/a n/a n/a phyrx 1 phy0rxdv [phy0crs1dv] 1.3[0.7] 1.3[1.3] n/a n/a n/a n/a phyrx 1 phy0rxerr[phy0rx0er] 1.3[0.7] 1.4[1.5] n/a n/a n/a n/a phyrx 1 phy0txclk[phy0refclk] n/a n/a n/a n/a n/a n/a 1, async hdlcex interface hdlcexrxclk n/a n/a n/a n/a n/a n/a hdlcexrxdataa:b 23.8 1.5 n/a n/a n/a n/a hdlcexrxfs 24.2 0.8 n/a n/a n/a n/a hdlcextxclk n/a n/a n/a n/a n/a n/a hdlcextxdataa:b n/a n/a 7.6 3.3 12 8 hdlcextxfs 24.2 0.8 n/a n/a n/a n/a hdlcextxena [gpio28][uart1_dcd ] n/a n/a 8.5 3.5 12 8 hdlcextxenb [gpio29][uart1_ri ] n/a n/a 8.9/ 3.8 12 8 internal peripheral interface iicscl async async async async 17 11 iicsda async async async async 17 11 [uart0_cts ] async async n/a n/a n/a n/a [uart0_dcd ] async async n/a n/a n/a n/a
advance information powernp tm npe405l embedded processor data sheet 45 [uart0_dsr ] async async n/a n/a n/a n/a [uart0_dtr ] n/a n/a async async 12 8 [uart0_ri ] async async n/a n/a n/a n/a [uart0_rts ] n/a n/a async async 12 8 uart0_rx async async n/a n/a n/a n/a uart0_tx n/a n/a async async 12 8 [uart1_cts ] async async n/a n/a n/a n/a [uart1_dcd ]gpio28 [hdlcextxena] async async n/a n/a n/a n/a [uart1_dsr ] async async n/a n/a n/a n/a [uart1_dtr ] n/a n/a async async 12 8 [uart1_ri ]gpio29 [hdlcextxenb] async async n/a n/a n/a n/a [uart1_rts ] n/a n/a async async 12 8 uart1_rx async async n/a n/a n/a n/a uart1_tx n/a n/a async async 12 8 uartserclk async async n/a n/a n/a n/a interrupts interface [irq0:6]gpio17:23 async async n/a n/a n/a n/a jtag interface tck async async n/a n/a n/a n/a tdi async async n/a n/a n/a n/a tdo n/a n/a async async 12 8 tms async async n/a n/a n/a n/a trst async async n/a n/a n/a n/a system interface [trcclk]gpio0 n/a n/a 8.7 1.2 12 8 [ts1e]gpio1 n/a n/a 5.8 1.2 12 8 [ts2e]gpio2 n/a n/a 5.7 1.2 12 8 [ts1o]gpio3 n/a n/a 5.3 1.0 12 8 [ts2o]gpio4 n/a n/a 5.3 1.0 12 8 [ts3]gpio5 n/a n/a 5.3 1.0 12 8 [ts4]gpio6 n/a n/a 5.3 1.0 12 8 [ts5]gpio7 n/a n/a 5.4 1.0 12 8 [ts6]gpio8 n/a n/a 5.3 1.0 12 8 gpio30 async async async async 12 8 halt async async n/a n/a n/a n/a i/o speci?ations?66mhz (part 2 of 3) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum)
advance information powernp tm npe405l embedded processor data sheet 46 sysclk n/a n/a n/a n/a n/a n/a syserr n/a n/a 5.3 1.7 12 8 sysreset n/a n/a n/a n/a 12 8 testen dc dc n/a n/a n/a n/a tmrclk n/a n/a async async n/a n/a sdram interface ba1:0 n/a n/a 5.5 1.5 19 12 sysclk 1, 2 bankse 3:0 n/a n/a 4.6 1.0 19 12 sysclk 2 cas n/a n/a 5.3 1.4 19 12 sysclk 1, 2 clken0:1 n/a n/a 3.9 1.0 40 25 sysclk 2 dqm3:0 n/a n/a 4.7 1.0 19 12 sysclk 2 dqmcb n/a n/a 4.7 1.0 19 12 sysclk 2 ecc7:0 1.8 0.3 4.5 1.0 19 12 sysclk 2 memaddr12:0 n/a n/a 5.5 1.4 19 12 sysclk 1, 2 memclkout0:1 n/a n/a 0.4 -1.2 19 12 sysclk 2, 3 memdata31:0 1.8 0.3 4.4 1.0 19 12 sysclk 2 ras n/a n/a 5.7 1.6 19 12 sysclk 1, 2 we n/a n/a 5.4 1.4 19 12 sysclk 1, 2 external slave peripheral interface dmareq0:3 [gpio9:12] 4.1 0.0 5.5 1.1 n/a n/a perclk dmaack0:3 [gpio13:16] n/a n/a 5.8 1.1 12 8 perclk eot0:3 [tc0:3 ] [gpio24:27] 3.7 -0.1 6.7 1.2 12 8 perclk peraddr4:31 n/a n/a 6.5 0.9 17 11 perclk perblast n/a n/a 5.6 1.4 12 8 perclk percs0:3 n/a n/a 5.5 1.3 12 8 perclk perdata0:15 3.9 1.0 7.1 1.0 17 11 perclk peroe n/a n/a 5.7 1.4 12 8 perclk perpar0:1 2.7 0.0 6.4 0.9 17 11 perclk perr/w n/a n/a 5.7 1.4 12 8 perclk perready 6.2 -0.5 n/a n/a n/a n/a perclk perwbe0: 1 n/a n/a 5.7 1.3 12 8 perclk perclk n/a n/a 0.5 -0.9 17 11 plb clk 4 pererr 3.5 -0.6 n/a n/a n/a n/a perclk perwe [gpio31] n/a n/a 7.0 1.3 12 8 i/o speci?ations?66mhz (part 3 of 3) notes: 1. ethernet interface meets timing requirements as defined by ieee 802.3 standard. 2. the two-cycle sdram command interface is driven in cycle 1 and used in cycle 2. output times in table are in cycle 1. 3. sdram output timing is relative to the rising edge of the internal plb clock, which is an integral multiple of and rising- edge aligned with sysclk. therefore, sdram output timings in the table are shown relative to sysclk. timings shown are for a lumped 50pf load, however the interface has been verified for pc100-compliant operation using transmission line circuit analysis. 4. sdram memclkout0:1 rising edge at package pin precedes the internal plb clock by approximately 0.5ns for a typical clock network or a lumped 10pf load. 5. perclk rising edge at package pin with a 10pf load trails the internal plb clock by approximately 0.8ns. signal input (ns) output (ns) output current (ma) clock notes setup time (minimum) hold time (minimum) valid delay (maximum) 50pf load hold time (minimum) 50pf load i/o h (maximum) i/o l (minimum)
advance information powernp tm npe405l embedded processor data sheet 47 initialization the following describes the method by which initial chip settings are established when a system reset occurs. pin strapping while the sysreset input pin is low (system reset), the state of certain i/o pins is read to enable default initial conditions prior to npe405l start-up. the actual capture instant is the nearest reference clock edge before the deassertion of reset. these pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. these pins are use for strap functions only during reset. they are used for other signals during normal operation. the following table lists the strapping pins along with their functions and strapping options. strapping pin assignments function option ball strapping width of boot device on ebc data bus y21 8 bits 0 16 bits 1 ethernet zmii mode v21 u20 mii mode 0 0 smii mode 0 1 rmii 10 mbps mode 1 0 rmii 100 mbps mode 1 1
advance information powernp tm npe405l embedded processor data sheet 48 (c) copyright international business machines corporation 1999, 2000 all rights reserved printed in the united states of america november 2000 the following are trademarks of international business machines corporation in the united states, or other countries, or both: other company, product, and service names may be trademarks or service marks of others. preliminary edition (11/22/00) this document contains information on a new product under development by ibm. ibm reserves the right to change or discontinue this product without notice. this document is a preliminary edition of the powernp npe405l data sheet . make sure you are using the correct edition for the level of the product. while the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. all information contained in this document is subject to change without notice. the products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of ibm or third parties. all information contained in this document was obtained in specific environments, and is presented as an illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52 hopewell junction, ny 12533-6351 the ibm home page is www. ibm.com . the ibm microelectronics division home is www.chips.ibm.com . sa14-2558-00 blue logic coreconnect ibm logo codepack ibm powerpc

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